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词汇
tristate logicTSL
释义
tristate logicTSL
在晶体管-晶体管逻辑电路中加上禁止输入的电路。在禁止输入为低电平时;电路有两种状态;即高电平和低电平;当禁止输入为高电平时;电路呈现第三种状态;即输出端为开路状态。
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更新时间:2025/7/11 14:35:57